#ifndef HW_I2C_H
#define HW_I2C_H


//*************************************************************************************************
//
// The following are defines for the I2C register offsets
//
//*************************************************************************************************
#define I2C_O_CON                       0x00U           // I2C control register
#define I2C_O_TAR                       0x04U           // I2C slave address(I2C tartget address)
#define I2C_O_OAR                       0x08U           // I2C own address
#define I2C_O_DATA_CMD                  0x10U           // I2C Receives/sends data buffers and commands
#define I2C_O_SS_SCL_HCNT               0x14U           // I2C Standard speed clock SCL high count
#define I2C_O_SS_SCL_LCNT               0x18U           // I2C Standard speed clock SCL low  count
#define I2C_O_FS_SCL_HCNT               0x1CU           // I2C Fast mode and Fast+ mode clock SCL high count
#define I2C_O_FS_SCL_LCNT               0x20U           // I2C Fast mode and Fast+ mode clock SCL low  count
#define I2C_O_INTR_STAT                 0x2CU           // I2C Interrupted status
#define I2C_O_INTR_MASK                 0x30U           // I2C interrupt mask
#define I2C_O_RAW_INTR_STAT             0x34U           // I2C raw interrupt status
#define I2C_O_RX_TL                     0x38U           // I2C Receive  FIFO threshold
#define I2C_O_TX_TL                     0x3CU           // I2C Transmit FIFO threshold
#define I2C_O_CLR_INTR                  0x40U           // I2C Clear combination and individual interrupts
#define I2C_O_CLR_RX_UNDER              0x44U           // I2C Clear RX_UNDER  interrupts
#define I2C_O_CLR_RX_OVER               0x48U           // I2C Clear RX_OVER   interrupts
#define I2C_O_CLR_TX_OVER               0x4CU           // I2C Clear TX_OVER   interrupts
#define I2C_O_CLR_RD_REQ                0x50U           // I2C Clear RD_REQ    interrupts
#define I2C_O_CLR_TX_ABRT               0x54U           // I2C Clear TX_ABRT   interrupts
#define I2C_O_CLR_RX_DONE               0x58U           // I2C Clear RX_DONE   interrupts
#define I2C_O_CLR_ACTIVITY              0x5CU           // I2C Clear ACTIVITY  interrupts
#define I2C_O_CLR_STOP_DET              0x60U           // I2C Clear STOP_DET  interrupts
#define I2C_O_CLR_START_DET             0x64U           // I2C Clear START_DET interrupts
#define I2C_O_CLR_GEN_CALL              0x68U           // I2C Clear GEN_CALL  interrupts
#define I2C_O_ENABLE                    0x6CU           // I2C enable
#define I2C_O_STR                       0x70U           // I2C status
#define I2C_O_TXFLR                     0x74U           // I2C Send FIFO level registers
#define I2C_O_RXFLR                     0x78U           // I2C Recv FIFO level registers
#define I2C_O_SDA_HOLD                  0x7CU           // I2C SDA hold time register
#define I2C_O_TX_ABRT_SOURCE            0x80U           // I2C Send abort status register
#define I2C_O_SLV_DATA_NACK_ONLY        0x84U           // I2C Generates the SLV_DATA_NACK register
#define I2C_O_SDA_SETUP                 0x94U           // I2C SDA setting register
#define I2C_O_ACK_GENERAL_CALL          0x98U           // I2C ACK bus broadcast register
#define I2C_O_FS_SPKLEN                 0xA0U           // I2C ISS and FS inhibit peak restriction


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CON register
//
//*************************************************************************************************
#define I2C_CON_MASTER_MODE             0x1U            // Control whether the master device is enabled.
#define I2C_CON_SPEED_S                 0x1U
#define I2C_CON_SPEED                   0x6U            // The Rate of the I2C interface working in master mode.
#define I2C_CON_10BITADDR_SLAVE         0x8U            // When used as a slave device, this bit controls whether to respond to a 7-bit or 10-bit address.
#define I2C_CON_10BITADDR_MASTER        0x10U           // Use 7-bit or 10-bit addressing mode when starting a transfer in master mode.
#define I2C_CON_RESTART_EN              0x20U           // Determines whether the RESTART condition can be sent when acting as the master device.
#define I2C_CON_SLAVE_DISABLE           0x40U           // Controls whether I2C disables its slave device.
#define I2C_CON_STOP_DET_IFADDRESSED    0x80U           // In slave mode: Whether to generate a STOP interrupt.
#define I2C_CON_TX_EMPTY_CTRL           0x100U          // This bit controls the generation of the TX_EMPTY interrupt.
#define I2C_CON_RX_FIFO_FULL_HLD_CTRL   0x200U          // This bit controls whether the receiving FIFO should hold the bus when it is physically filled to its RX_BUFFER_DEPTH.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C TAR register(I2C slave address or tartget address)
//
//*************************************************************************************************
#define I2C_TAR_TAR_S                   0x0U
#define I2C_TAR_TAR_M                   0x3FFU          // Slave Address: The target address in master mode.
#define I2C_TAR_GC_OR_START             0x400U          // This bit indicates whether I2C is executing the broadcast call or the start byte command.
#define I2C_TAR_SPECIAL                 0x800U          // This bit indicates how the soft General Call or byte command is started.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C OAR register(I2C own address)
//
//*************************************************************************************************
#define I2C_OAR_OAR_S                   0x0U
#define I2C_OAR_OAR_M                   0x3FFU          // Slave Address: The IC_SAR register holds the slave address when I2C is operated as a slave


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C DATA_CMD register
//
//*************************************************************************************************
#define I2C_DATA_CMD_DATA               0xFFU           // Receive or Transmit data
#define I2C_DATA_CMD_CMD                0x100U          // This bit controls whether a read(set 1) or write(set 0) operation is performed


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C SS_SCL_HCNT register
//
//*************************************************************************************************
#define I2C_SS_SCL_HCNT_S               0x0U
#define I2C_SS_SCL_HCNT                 0xFFFFU         // High level period of SCL clock in Standard mode


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C SS_SCL_LCNT register
//
//*************************************************************************************************
#define I2C_SS_SCL_LCNT_S               0x0U
#define I2C_SS_SCL_LCNT                 0xFFFFU         // Low level period of SCL clock in Standard mode


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C FS_SCL_HCNT register
//
//*************************************************************************************************
#define I2C_FS_SCL_HCNT_S               0x0U
#define I2C_FS_SCL_HCNT                 0xFFFFU         // High level period of SCL clock in Fast mode


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C FS_SCL_LCNT register
//
//*************************************************************************************************
#define I2C_FS_SCL_LCNT_S               0x0U
#define I2C_FS_SCL_LCNT                 0xFFFFU         // Low level period of SCL clock in Fast mode


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C INTR_STAT register(interrupt status register)
//
//*************************************************************************************************
#define I2C_ISTR_RX_UNDER               0x01U           // Receive buffer under interrupt status
#define I2C_ISTR_RX_OVER                0x02U           // Receive buffer over  interrupt status
#define I2C_ISTR_RX_FULL                0x04U           // Receive buffer full  interrupt status
#define I2C_ISTR_TX_OVER                0x08U           // Transmit buffer over interrupt status
#define I2C_ISTR_TX_EMPTY               0x10U           // Transmit buffer empty interrupt status
#define I2C_ISTR_RD_REQ                 0x20U           // Read request interrupt status
#define I2C_ISTR_TX_ABRT                0x40U           // Transmit abort interrupt status
#define I2C_ISTR_RX_DONE                0x80U           // When i2c as a slave-transmitter, the master does not acknowledge a transmitted byte, this bit set to 1.
#define I2C_ISTR_ACTIVITY               0x100U          // This bit captures the active state of the I2C interface and holds the Settings until cleared.
#define I2C_ISTR_STOP_DET               0x200U          // Whether a STOP condition has occurred.
#define I2C_ISTR_START_DET              0x400U          // Whether a START or RESTART condition has occurred
#define I2C_ISTR_GEN_CALL               0x800U          // Set only when a General Call address is received and it is acknowledged.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C INTR_MASK register(interrupt mask register)
//
//*************************************************************************************************
#define I2C_IMASK_RX_UNDER              0x01U           // Mask
#define I2C_IMASK_RX_OVER               0x02U           // Mask
#define I2C_IMASK_RX_FULL               0x04U           // Mask
#define I2C_IMASK_TX_OVER               0x08U           // Mask
#define I2C_IMASK_TX_EMPTY              0x10U           // Mask
#define I2C_IMASK_RD_REQ                0x20U           // Mask
#define I2C_IMASK_TX_ABRT               0x40U           // Mask
#define I2C_IMASK_RX_DONE               0x80U           // Mask
#define I2C_IMASK_ACTIVITY              0x100U          // Mask
#define I2C_IMASK_STOP_DET              0x200U          // Mask
#define I2C_IMASK_START_DET             0x400U          // Mask
#define I2C_IMASK_GEN_CALL              0x800U          // Mask


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C RAW_INTR_STAT register(raw interrupt status register)
//
//*************************************************************************************************
#define I2C_RAW_ISTR_RX_UNDER           0x01U           // Raw 
#define I2C_RAW_ISTR_RX_OVER            0x02U           // Raw 
#define I2C_RAW_ISTR_RX_FULL            0x04U           // Raw 
#define I2C_RAW_ISTR_TX_OVER            0x08U           // Raw 
#define I2C_RAW_ISTR_TX_EMPTY           0x10U           // Raw 
#define I2C_RAW_ISTR_RD_REQ             0x20U           // Raw 
#define I2C_RAW_ISTR_TX_ABRT            0x40U           // Raw 
#define I2C_RAW_ISTR_RX_DONE            0x80U           // Raw 
#define I2C_RAW_ISTR_ACTIVITY           0x100U          // Raw 
#define I2C_RAW_ISTR_STOP_DET           0x200U          // Raw 
#define I2C_RAW_ISTR_START_DET          0x400U          // Raw 
#define I2C_RAW_ISTR_GEN_CALL           0x800U          // Raw 


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C RX_TL register(Receive FIFO Threshold Level)
//
//*************************************************************************************************
#define I2C_RX_TL                       0xFFU           // Receive FIFO threshold level, Control RX_FULL interrupt triggered


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C TX_TL register(Transmit FIFO Threshold Level)
//
//*************************************************************************************************
#define I2C_TX_TL                       0xFFU           // Transmit FIFO threshold level, Control TX_EMPTY interrupt triggered


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_INTR register(Clear interrupt)
//
//*************************************************************************************************
#define I2C_CLR_INTR                    0x01U           // Reading this register will clear all combined interrupts and independent interrupts


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_RX_UNDER register
//
//*************************************************************************************************
#define I2C_CLR_RX_UNDER                0x01U           // Reading this register clears the RX_UNDER interrupt (bit 0) in the IC_RAW_INTR_STAT register


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_RX_OVER register
//
//*************************************************************************************************
#define I2C_CLR_RX_OVER                 0x01U           // Reading this register clears the RX_OVER interrupt (bit 1) in the IC_RAW_INTR_STAT register.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_TX_OVER register
//
//*************************************************************************************************
#define I2C_CLR_TX_OVER                 0x01U           // Reading this register clears the TX_OVER interrupt (bit 3) in the IC_RAW_INTR_STAT register.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_RD_REQ register
//
//*************************************************************************************************
#define I2C_CLR_RD_REQ                  0x01U           // Reading this register clears the RD_REQ interrupt (bit 5) in the IC_RAW_INTR_STAT register.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_TX_ABRT register
//
//*************************************************************************************************
#define I2C_CLR_TX_ABRT                 0x01U           // Reading this register clears the TX_ABRT interrupt (6th bit) in the IC_RAW_INTR_STAT register, as well as the IC_TX_ABRT_SOURCE register


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_RX_DONE register
//
//*************************************************************************************************
#define I2C_CLR_RX_DONE                 0x01U           // Reading this register clears the RX_DONE interrupt (bit 7) in the IC_RAW_INTR_STAT register.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_ACTIVITY register
//
//*************************************************************************************************
#define I2C_CLR_ACTIVITY                0x01U           // Reading this register gets the status of the ACTIVITY interrupt (8th bit) in the IC_RAW_INTR_STAT register


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_STOP_DET register
//
//*************************************************************************************************
#define I2C_CLR_STOP_DET                0x01U           // Reading this register clears the STOP_DET interrupt (bit 9) in the IC_RAW_INTR_STAT register.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_START_DET register
//
//*************************************************************************************************
#define I2C_CLR_START_DET               0x01U           // Reading this register clears the START_DET interrupt (bit 10) in the IC_RAW_INTR_STAT register


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C CLR_GEN_CALL register
//
//*************************************************************************************************
#define I2C_CLR_GEN_CALL                0x01U           // Reading this register clears the GEN_CALL interrupt (bit 11) in the IC_RAW_INTR_STAT register


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C ENABLE register
//
//*************************************************************************************************
#define I2C_EN_ENABLE                   0x01U           // The I2C module is enabled
#define I2C_EN_ABORT                    0x02U           // When the I2C module is used as the Master device, the software can set this bit to abort the I2C transmission.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C STR register(I2C Status Read-Only register)
//
//*************************************************************************************************
#define I2C_STR_ACTIVITY_S              0x0U
#define I2C_STR_ACTIVITY_M              0x1U            // I2C activity status
#define I2C_STR_TFNF                    0x2U            // I2C Transmit FIFO not full status
#define I2C_STR_TFE                     0x4U            // I2C Transmit FIFO completely empty status
#define I2C_STR_RFNE                    0x8U            // I2C Receive FIFO not full status
#define I2C_STR_RFF                     0x10U           // I2C Receive FIFO fully full status
#define I2C_STR_MST_ACTIVITY            0x20U           // I2C Master FSM active
#define I2C_STR_SLV_ACTIVITY            0x40U           // I2C Slave  FSM active


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C TXFLR register(I2C Transmit FIFO level registers)
//
//*************************************************************************************************
#define I2C_TXFLR_S                     0x0U
#define I2C_TXFLR                       0x1FU           // I2C Transmit FIFO level registers. Contains the number of valid data entries in the Transmit FIFO


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C RXFLR register(I2C Receive FIFO level registers)
//
//*************************************************************************************************
#define I2C_RXFLR_S                     0x0U
#define I2C_RXFLR                       0x1FU           // I2C Receive FIFO level registers. Contains the number of valid data entries in the Receive FIFO


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C SDA_HOLD register(I2C SDA Hold Time register)
//
//*************************************************************************************************
#define I2C_SDA_HOLD_TX_S               0x0U
#define I2C_SDA_HOLD_TX                 0xFFFFU         // When I2C acting as a transmitter, set the required SDA hold time in ic_clk cycles.
#define I2C_SDA_HOLD_RX_S               0x16U
#define I2C_SDA_HOLD_RX                 0xFF0000U       // When I2C acting as a receiver,    set the required SDA hold time in ic_clk cycles.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C TX_ABRT_SOURCE register(I2C transfer abort source register)
//
//*************************************************************************************************
#define I2C_ABRT_7B_ADDR_NOACK          0x1U            // The Master is in 7-bit address mode, and the sent address is not acknowledged by any slave
#define I2C_ABRT_10ADDR1_NOACK          0x2U            // The Master is in 10-bit address mode, and the first 10-bit address byte is not acknowledged by any slave
#define I2C_ABRT_10ADDR2_NOACK          0x4U            // The Master is in 10-bit address mode, and the second address byte of the 10-bit address is not acknowledged by any slave
#define I2C_ABRT_TXDATA_NOACK           0x8U            // The Master received the acknowledgement of the address, but did not receive the acknowledgement from the remote slave when sending the data byte after the address
#define I2C_ABRT_GCALL_NOACK            0x10U           // The I2C interface sent a broadcast notification in master mode, but no slave on the bus acknowledged the broadcast notification
#define I2C_ABRT_GCALL_READ             0x20U           // The I2C interface sends a broadcast notification in main mode, but the user programs the bytes after the broadcast notification to read from the bus (IC_DATA_CMD[9] is set to 1).
#define I2C_ABRT_SBYTE_ACKDET           0x80U           // The Master sent a START byte, and the START byte was acknowledged (error behavior)
#define I2C_ABRT_SBYTE_NORSTRT          0x200U          // The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte.
#define I2C_ABRT_10B_RD_NORSTRT         0x400U          // The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode
#define I2C_ABRT_MASTER_DIS             0x800U          // User tries to initiate a Master operation with the Master mode disabled
#define I2C_ARB_LOST                    0x1000U         // The Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.
#define I2C_ABRT_SLVFLUSH_TXFIFO        0x2000U         // Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO
#define I2C_ABRT_SLV_ARBLOST            0x4000U         // Slave lost the bus while transmitting data to a remote master
#define I2C_ABRT_SLVRD_INTX             0x8000U         // When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register
#define I2C_ABRT_USER_ABRT              0x10000U        // This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]).
#define I2C_TX_FLUSH_CNT                0xFF800000U     // Bits[31:23] This field indicates the number of Tx FIFO data commands that are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C SLV_DATA_NACK_ONLY register(Generate Slave Data NACK Register)
//
//*************************************************************************************************
#define I2C_SLV_DATA_NACK_ONLY_NACK     0x01U           // Generate Slave Data NACK, I2C is acting as a slave-receiver


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C SDA_SETUP register(SDA Setup Register)
//
//*************************************************************************************************
#define I2C_SDA_SETUP                   0xFFU           // SDA Setup


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C ACK_GENERAL_CALL register(ACK General Call Register)
//
//*************************************************************************************************
#define I2C_ACK_GENERAL_CALL            0x01U           // ACK General Call, only available when in slave mode


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2C FS_SPKLEN register(I2C SS and FS Spike Suppression Limit Register)
//
//*************************************************************************************************
#define I2C_FS_SPKLEN_S                 0x0U
#define I2C_FS_SPKLEN                   0xFFU           // This register must be set before any I2C bus transaction can take place to ensure stable operation


#endif
